What is the state of I/O while FPGA is in the process of configuration?
After system reset, FPGA will download the data from flash-rom(configuration). This process will take some time. In the time, What is the I/O state? "1"? "0"? or "Z"? This state will (badly) effect the peripheral IC?
Note: My PFGA is the one of Altera Cyclone Family, EP1C20F400C6.
All FPGAs pins are tri-stated during the configuration. And since most of the FPGAs now a days have a 100k pullup resistor, the I/Os are all '1's without connections, those with connections are different depending on your application.
All FPGAs pins are tri-stated during the configuration. And since most of the FPGAs now a days have a 100k pullup resistor, the I/Os are all '1's without connections, those with connections are different depending on your application.
It depends on your devices. Iad problem with FPGAs causing srange behaviour on periferal components based on the start up issues. Thats why it is important to add pull down resistors to any component that needs a solid '0' while the FPGA is configuring (can take a long time after the VCC is stable).
In most cases, this is not a problem, but it is better to be safe than chasing a ghoast problem for days (or weeks).