ruwan2
Member level 5
Hi,
I read the following about Verilog expression:
Example 4-1
shows two ways to write the expression “minus 12 divided by 3.” Note
that -12 and -d12 both evaluate to the same bit pattern, but in an
expression -d12 loses its identity as a signed, negative number.
I do not know what the same bit pattern means.
I got it. It means that "-12 and -'d12"
I read the following about Verilog expression:
Example 4-1
shows two ways to write the expression “minus 12 divided by 3.” Note
that -12 and -d12 both evaluate to the same bit pattern, but in an
expression -d12 loses its identity as a signed, negative number.
I do not know what the same bit pattern means.
I got it. It means that "-12 and -'d12"
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