Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

What is the role of Multiples in mos transistors??

Status
Not open for further replies.

amic

Member level 5
Joined
Aug 30, 2005
Messages
91
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
2,069
I can implement W/L = 12/1 with 1 multiple ( m =1) or with 4 multiples ( m=4) with each W/L= 3/1....?

HOW WOULD THE DESIGN CHANGE ? WHAT EFFECTS THESE MULTIPLES HAVE ON MOSFET OPERATIONS ?

 

v_c

Advanced Member level 2
Joined
Oct 11, 2005
Messages
514
Helped
113
Reputation
226
Reaction score
37
Trophy points
1,308
Location
Chicago, IL, USA
Activity points
8,229
Ideally, the multiple small transistors should operate like one large transistor. Realistically, it all depends on how the transistor parameters and parasitics scale. In the case with multiple transistors, each device will see a integer portion of the current in the large device. So if everything scales linearly, then operation should be identical. However, I doubt if this is the case! Device parameters are probably nonlinear function of the bias voltages and currents, so you will probably get different behavior. But depending on how strong the nonlinearity is the results may be close. Just try it and beware of the results.

Best regards,
v_c
 
Last edited by a moderator:

eda_freak

Member level 3
Joined
Jun 20, 2005
Messages
62
Helped
12
Reputation
24
Reaction score
2
Trophy points
1,288
Activity points
1,997
hi,

one thing that effects is usage of large trasistors is huge parasitics attached to it...
multiple fingers reduce parasitics...i.e. capacitiance reduces in series....and then awkwardly sized transisors are huge problem in layouts...two reasons that corroborate using fingers...
 

venkateshr

Member level 3
Joined
Feb 1, 2005
Messages
63
Helped
3
Reputation
6
Reaction score
1
Trophy points
1,288
Activity points
503
Hi ,
In real world they realize heavy width trans. as combination of fingers where the diffusions (drain/source)are shared thereby bringing down the parasitics as said above and also the layout will be better and one more fact is that the contact resistances will come down thereby improvising the freq. response.

thanks
 

amic

Member level 5
Joined
Aug 30, 2005
Messages
91
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
2,069
ok. Let me apply this knowledge to my design....
I have a opamp with 3 types of devices....tail current source, input pair and loads...now where exactly i need to use more multiples and where min. possible.

1. Input pair..i think..should have multipliers coz that will reduce parasitic cap.
2. tail current source would anyway need multipliers ...since matching is required.
3. what about loads ??
 

rfsystem

Advanced Member level 3
Joined
Feb 25, 2002
Messages
914
Helped
148
Reputation
292
Reaction score
38
Trophy points
1,308
Location
Germany
Activity points
9,548
In practice there is a technology limt for for maximum W. That is because of current distribution instability. So high W should be spilt up by the product M*W. The dilemma is that sharing source /drain regions could reduce parasitics in the ideal case by about half. But if you simulate the parallel factor M, it is simulated as individual devices, not shared source/drain regions. But to wait for the layout is not right simulation strategy if you know in advance the difference. So if you have a schematic system where the source/drain areas are calulated and the result is netlisted. Or you use a subcircuit where the source/drain area is calulate within the subcircuit.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top