What is the relationship of noise and cmos scaling?

[John Xu]

noise vs. cmos scaling?

hi,
I have a question on the relatioonship between the noise characteristcs and the cmos process scaling. I intend to design a TIA(155M) and 0.6um and 0.35um mixed cmos process are availble. I just want to know, from the view of noise improvement, which process is better?

Scaled process means better or worse noise?

Thanks

 

[OpAmp]

noise vs. cmos scaling?

Analog design is full of different trade-offs. In my view, you can not say which process is better until you design the circuit in both technologies and see which one is less noisy. What I can say from basic formulas of noise in CMOS technologies is that, usually by scaling the noise of the process will increase. For example, thermal noise of a mosfet is 4*K*T*(Gamma)*gm. Gamma is usually 2/3 in long-channel transistors, while in submicron processes, it can be up to 2.5 (in 0.25um). But remember, still there is gm which may be different in two different technologies.
From another point of view, look at the flicker noise of a CMOS transistor which is: K/(Cox*WL*f). In a submicron technology, WL is less, but Cox is more. Also K may be different in both technologies, so you can not easily say which one has less noise.

 

[Syukri]

Re: noise vs. cmos scaling?

Agree with OP Amp..

The circuit it selft play a great rolll...Noise is different from a type of Analog circuit to another...

Rather than physical matters of increasing Cox i scaled CMOS, the dsign is vital...Like differential AMp the CM level must match to eleiminate noise in output signal...

In scaled device the standby power is also a big problem..