fifo18 virtex5 problem
It probably saved some silicon in the FIFO's pipeline, or improved speed.
Words from the Virtex-5 User Guide:
Reset
Reset is an asynchronous signal for multi-rate FIFO, and synchronous for synchronous FIFO. Reset must be asserted for three cycles to reset all read and write address counters and initialize flags after power up. Reset does not clear the memory, nor does it clear the output register. When reset is asserted High, EMPTY and ALMOST_EMPTY will be set to 1, FULL and ALMOST_FULL will be reset to 0. The reset signal must be High for at least three read clock and write clock cycles to ensure all internal states are reset to the correct values. During RESET, RDEN and WREN must be held Low.