[SOLVED] What is the purpose of AMBA AHB Burst transfer

[Endre]

Hi,

What is the advantage of burst transfer over repeated single transfers? As I understand the burst mode is not faster. Than what's the aim of it?

 

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You should read the AMBA spec. As you don't specify which of the numerous versions. Taken from the original '99 version (found on another site):

Every transfer consists of:
• an address and control cycle
• one or more cycles for the data.

Therefore if you do single transfers every one of them have the overhead of the address and control cycle. It's significantly slower than burst transfers, which have a single address control cycle followed by a burst of data.

 

[Endre]

You should read the AMBA spec
Therefore if you do single transfers every one of them have the overhead of the address and control cycle. It's significantly slower than burst transfers, which have a single address control cycle followed by a burst of data.

I think no.
The address and data cycles are overlapped, pipelined. The data cycle is also the address cycle of the next transfer.

See the following document: IHI0011A_AMBA_SPEC.pdf, AMBA Specification (Rev 2.0)

Chapter 3.4 Basic transfer

"This simple example demonstrates how the address and data phases of the transfer occur
during different clock periods. In fact, the address phase of any transfer occurs during
the data phase of the previous transfer. This overlapping of address and data is
fundamental to the pipelined nature of the bus and allows for high performance
operation, while still providing adequate time for a slave to provide the response to a
transfer."

See: Figure 3-5 Multiple transfers

One single transfer takes 2 bus cycles, but e.g. 4 single transfers take 5 bus cycles (not 8) due to the overlapping.

I still don't understand why the burst transfer is faster.

 

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The address and data cycles are overlapped, pipelined. The data cycle is also the address cycle of the next transfer.

See the following document: IHI0011A_AMBA_SPEC.pdf, AMBA Specification (Rev 2.0)

Chapter 3.4 Basic transfer

"This simple example demonstrates how the address and data phases of the transfer occur
during different clock periods. In fact, the address phase of any transfer occurs during
the data phase of the previous transfer. This overlapping of address and data is
fundamental to the pipelined nature of the bus and allows for high performance
operation, while still providing adequate time for a slave to provide the response to a
transfer."

See: Figure 3-5 Multiple transfers

One single transfer takes 2 bus cycles, but e.g. 4 single transfers take 5 bus cycles (not 8) due to the overlapping.

I still don't understand why the burst transfer is faster.

I'll admit I just browsed Section 3 of the spec. I now see that it's not all that similar to AXI4 (which is what I've used in the past, though the spec mentions backward compatibility to AHB in that spec.

I would suspect if designed properly a burst transfer to a device with a fixed latency would result in a faster transfer than using single cycles.
Suppose the slave device requires a fixed latency before an address applied produces data that can be read. To hold off the data capture at the master the HREADY is not asserted until the data is ready. This subsequently results in the next address in a single cycle transfer to be held for multiple clock cycles (the clock cycles of latency). A burst transfer (if the slave supports such) would instead only have a single address cycle followed by the fixed latency followed by multiple data cycles.

You're thinking only in terms of a single cycle access that always returns data on the following clock cycle. For that the single (overlapping) and burst transfers take the same number of cycles. For a properly designed slave that supports burst transfers any latency in decoding of the address (think DDR SDRAM) would be absorbed in the HREADY hold off of the data cycle and the data cycles can be burst from the slave.