Power on Reset
power on reset provide initial reset for chip,
another important signal is "Power OK"
or UVLO (under volt lock out) ,
many chip must be ensure power > some volt
just can work , like latch (2 invert feed back ltach) cell will work on Vcc < 3v
, if no power_ok signal maybe system board (motherboard) have leakage current
cause chip have unstable volt (maybe 1~2v) , I ever meet this issue becuase my
chip must latch some initial state . finally I add power_ok signal remove it .
some system have power_on_reset signal , but never use power_ok , like 8051 system , maybe 8051 will detect outside latch signal , no power_ok will cause 8051 get wrong message .
Added after 2 minutes:
by the way , power_ok is difficut design than Power_on_reset , becuase power_ok need accuracy volt for reference like Vcc=4.5v , but when power ramp_up at this time , bandgap maybe not work well will create "fake" power_ok signal .