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"parasitic extraction" means : get the RC after your layout drawing complete,and add the parasitic of RC to simulate your circuit again to see its' performance aslo meet your spec. am i right?
thanks.
baggio
Ok, I have designed the VCO and for schematic simulation it can be run for 4GHz, then I convert the schematic into layout and did parasitic extraction, simulated again but its can only run till 3.5GHz (because of the extracted RC).
Do you have any suggestion, to fix the problem? Do I need to reduce the RC on the connection or better for me to change the transistor width layout or both?
Arghhhh. It is tedious to changed the layout because I used custom layout
Most of the analog layouts are hand-drawn..
dont worry.. its quite normal where you fix the design after post-layout simulations and then end up changing the layout.
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