[SOLVED] What is the meaning of "not synthesizable" in verilog?

[iVenky]

What is the meaning of "not synthesizable" in VHDL?

I am new to VHDL. I see that certain datatypes are synthesizable and some or not synthesizable. What do you mean by "synthesizable" ? Why certain datatypes are not synthesizable?

Thanks in advance.

 

[TrickyDicky]

Given your previous post asked about verilog and you posted a load of VHDL, I assume you're refering to VHDL here too?
Do you have any types in mind? most types are synthesisable. The only main one that I can think of is not is type time and real.

---------- Post added at 20:39 ---------- Previous post was at 20:38 ----------

synthesis is the conversion of code to primitive parts (like gates and registers). Its more the behaviour of the code that is important rather than the data types.

 

[iVenky]

Given your previous post asked about verilog and you posted a load of VHDL, I assume you're refering to VHDL here too?
Do you have any types in mind? most types are synthesisable. The only main one that I can think of is not is type time and real.

---------- Post added at 20:39 ---------- Previous post was at 20:38 ----------

synthesis is the conversion of code to primitive parts (like gates and registers). Its more the behaviour of the code that is important rather than the data types.

It's says higher dimensional arrays are not synthesizable.


Standard Logic is synthesizable.

I need some more explanation.

Thanks

 

[FvM]

I need some more explanation.

As said, you should ask clearer questions.

Structured VHDL datatypes, e.g. arrays, are not restricted in synthesis.

VHDL is a hardware description language, used both for simulation and synthesis purposes. Not synthesizable are those language constructs, that can't be represented by real hardware. This involves abstract language elements that can't be synthesized in any hardware, e.g. the real data type, or constructs that can't be mapped to a specific hardware platform used in synthesis, e.g. FFs triggered at both edges, asynchronous RAM for most programmable logic devices.