Jul 25, 2014 #1 B Bhuvana Eshwari Newbie level 3 Joined Sep 30, 2013 Messages 3 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 16 what is the major difference between verilog HDL and VHDL???? Which is best in designing the AMBA AHB, ASB,APB,AXI?????
what is the major difference between verilog HDL and VHDL???? Which is best in designing the AMBA AHB, ASB,APB,AXI?????
Jul 25, 2014 #2 ads-ee Super Moderator Staff member Joined Sep 10, 2013 Messages 7,944 Helped 1,822 Reputation 3,654 Reaction score 1,808 Trophy points 1,393 Location USA Activity points 60,208 Bhuvana Eshwari said: what is the major difference between verilog HDL and VHDL???? Which is best in designing the AMBA AHB, ASB,APB,AXI????? Click to expand... The biggest difference is VHDL's a strongly typed language and is significantly more verbose than Verilog. Either language will work well at implementing any if those bus protocols. Both languages are capable HDLs. Regards
Bhuvana Eshwari said: what is the major difference between verilog HDL and VHDL???? Which is best in designing the AMBA AHB, ASB,APB,AXI????? Click to expand... The biggest difference is VHDL's a strongly typed language and is significantly more verbose than Verilog. Either language will work well at implementing any if those bus protocols. Both languages are capable HDLs. Regards