what is the major difference between verilog HDL and VHDL????

[Bhuvana Eshwari]

what is the major difference between verilog HDL and VHDL????
Which is best in designing the AMBA AHB, ASB,APB,AXI?????

 

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what is the major difference between verilog HDL and VHDL????
Which is best in designing the AMBA AHB, ASB,APB,AXI?????

The biggest difference is VHDL's a strongly typed language and is significantly more verbose than Verilog.

Either language will work well at implementing any if those bus protocols. Both languages are capable HDLs.

Regards