here there's some tips:
"When reducing the gate length of an MOS transistor, the depletion regions around the source and drain have also to be reduced, to avoid effects such as charge sharing and punchthrough. To scale down the depletion regions, the doping oncentration of the substrate can be increased and the biases applied (i.e. the supply voltage) can be reduced.
The increase in the substrate doping also increases the threshold voltage, and this makes it more difficult to turn on the device. To compensate for this the gate oxide thickness is reduced."