A latch is only a primitive memory element. It is transparent under certain conditions and this can cause problems for designers who don't fully appreciate the limited functionality of the latch. Making sure your code produces real flip flops is considered good design practice.
Hi,
there is no differnece in inputs and outputs oa latch and FLIP FLOP.
the difference is only how they work
as far as effect of latch is concerened...it will behave accordingly
Sorry ppl, but my quastion was not about the differents between LATCH and FF.
I was about the cases where a LATCH is prdoced during uncovered all the combination of Asynchrinous process such as MUX, CASE, FSM
my quastions:
1. Where the LATCH is located/genrated? What is the input and the outputs of the LATCH?
2. Supposed 4:1 MUX statement while in the VERILOG we consider ONLY THREE conditions. whats happend exactlly with the FOURTH conditon? how it treated??? If LATCH is already produced so what its effect?
module latch (en, d, q);
if (en == 1'b1)
q <= d;
endmodule
This is not a real Verilog module, it's just to show you. As you can see, you have only told the system what you want to happen when en is 1. You haven't told the system what to do when en is 0, or when clock is is rising or when reset is falling, etc. So the synthesizer or simulator can only produce a simple latch with this information.
module latch (en, d, q);
if (en == 1'b1)
q <= d;
endmodule
This is not a real Verilog module, it's just to show you. As you can see, you have only told the system what you want to happen when en is 1. You haven't told the system what to do when en is 0, or when clock is is rising or when reset is falling, etc. So the synthesizer or simulator can only produce a simple latch with this information.
Please correct me!
It means that the MACHINE will remeber always the recent state.
That recent state is unwanted/unexpected so maybe something wrong with the next state if the input is changed because it will not success to decode the next-state.