Re: Regarding ModelSim
it is the file which contains the initial condition values...
vhdl, verilog version used
project settings, all the library file locations used...
it may be work, unisim, simprim etc..
we can change and add on our requirements..that any logical library we can map by changing this name
Added after 28 seconds:
it is the file which contains the initial condition values...
vhdl, verilog version used
project settings, all the library file locations used...
it may be work, unisim, simprim etc..
we can change and add on our requirements..that any logical library we can map by changing this name