What is the importance of assertion in verification

[karalamoorthy_p]

Hi All,

I am new in SVA. Please I want exact usage of assertions. Because in all materials having explain like this, assertions are mainly used to test the behavior of the design.

But in verification, we have added lot of checks to find the bugs. Then why we have to use assertion additionally.

One more thing, Is SVA is compulsory for verification?

Suppose cant we check our design without SVA?

Please solve these clarification. If anyone knows please reply back soon. It would be very helpful.

Thanks.

 

[dave_59]

To say that an assertion is mainly used to test the behavior of a design is a very simplistic view of what an an assertion can do. Assertions are used to capture requirements and assumptions in a form independent of the implementation.

Suppose you have the requirement that GRANT must occur within 3 cycles of a REQUEST. You can write an assertion that checks this each time you run a test, but you also get a coverage point that tells you if your test actually produced a REQUEST and received a GRANT within 3 cycles. That way you get get a report on what your tests are check and get metrics on which tests are the most effective for checking all your assertions. That can significantly improve the performance of your regression suite of test. Yes, you could do this without using SVA, but this gives you a standard way of doing it and tools to collect and analyze the data.

Another thing assertions can do for you that would be very difficult to do without SVA is to formally prove an assertion. If your design takes REQUEST as an input and produces GRANT as an output, is it possible for it to take more than 3 cycles to produce GRANT? A formal checking tool can verify the assertion and generate a scenario where it could take longer.

If used by the designer, assertions can indicate intent or assumptions about the design. Maybe for this particular design, they know that GRANT will always come 1 cycle after REQUEST, and the RTL was written to expect that. The designer would put in an assertion which is essentially an executable comment that say this design works only if the following assertions are true.

For more information, please see: https://verificationacademy.com/courses/assertion-based-verification

 

[karalamoorthy_p]

Thank you so much Dave.

 

[nirmish]

hi

Assertion are basically used for checking correctness in behavior of control signals. Data path are verified using scoreboards.

Assertions can be used by both RTL designer or Verification guys.

simplest example can be given as : to check the relation between the req and ack signal.

This can be done in conventional manner also, but that may require lot of efforts to do so. but using assertion it can be done very easily as it has already defined so many construct to do so. details can be found in LRM.

Assertions are new, is just that i was not there in verilog, otherwise VHDL always has assertions.

hope this helps

 

[dave_59]

I believe what nirmish is trying to say when people talk SystemVerilog Assertions (SVA), they are usually referring to checking a sequence of conditions over a period of time, or temporal protocol checking. That is the main purpose of SVA. A scoreboard is another form of an assertion using procedural code.

The assert statement in VHDL is known as an immediate assertion in SVA - a simple check of a single Boolean condition. It does not handle the temporal checking that SVA has.