May 6, 2010 #1 S simplybharath Junior Member level 2 Joined Apr 22, 2009 Messages 21 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,281 Activity points 1,400 hi all , can anyone explain what is a half cycle datapath ?? thank you
May 6, 2010 #2 D D Saurabh Junior Member level 1 Joined Jun 3, 2009 Messages 18 Helped 4 Reputation 8 Reaction score 0 Trophy points 1,281 Location Singapore Activity points 1,396 half cycle path a path where the data is launched by a FF on posedge of a clock and captured by a FF on negedge, hence the time available is only half a cycle instead of full cycle where both FF are working on posedge
half cycle path a path where the data is launched by a FF on posedge of a clock and captured by a FF on negedge, hence the time available is only half a cycle instead of full cycle where both FF are working on posedge
May 6, 2010 #3 S simplybharath Junior Member level 2 Joined Apr 22, 2009 Messages 21 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,281 Activity points 1,400 half cycle path ok , where are this kind of paths used generally ?? whats the logic associated and y ?
half cycle path ok , where are this kind of paths used generally ?? whats the logic associated and y ?
May 7, 2010 #4 M muni123 Member level 3 Joined Apr 28, 2007 Messages 64 Helped 4 Reputation 8 Reaction score 2 Trophy points 1,288 Location India Activity points 1,625 half cycle path I guess these types of data paths are figured out in Latch based designs, where data is captured only when the clock is 1. Correct me if I'm wrong.
half cycle path I guess these types of data paths are figured out in Latch based designs, where data is captured only when the clock is 1. Correct me if I'm wrong.
May 7, 2010 #5 R raju3295 Full Member level 4 Joined Jan 4, 2007 Messages 205 Helped 17 Reputation 34 Reaction score 4 Trophy points 1,298 Activity points 2,376 half cycle path generally we have architecture like ram->lat-> reg here ram is a neg edged and lat is +ve edged one, so ram to lat is a half cycle path
half cycle path generally we have architecture like ram->lat-> reg here ram is a neg edged and lat is +ve edged one, so ram to lat is a half cycle path