May be this Eg. helps you out.......
E.g.: 133 MHz CL3 Device (7.5 ns per cycle, 3 cycle request latency)
100 MHz CL2 Device (10 ns per cycle, 2 cycle request latency)
First Bit would be available after :
Case 1 : 22.5 ns (7.5 * 3)
Case 2 : 20 ns (10 * 2)
So, it can be stated as LOWER Latency BETTER Performance.
But,With a Burst Reading Capability of 6 bits.
Case 1 : 60 ns (7.5 * 3 latency + 7.5 * 5 after first)
Case 2 : 70 ns (10 * 2 latency + 10 * 5 after first)
So,it can be stated that HIGHER Clock Speed Wins.