1- you could write a model for your black box (fastscan model) or fastscan is able to read verilog "model". We used it for our analog views, with very simplest description. All outputs are define at the expected values when the design will be in scan.
2-you can not "remove" untestable fault. The tool anaylze the fault list and some are not accessible, some are "merge" with others.... To increase the coverage, you could add some test points, or loop-back around or inside the black box (if you could).