Re: what is the diffirence between bit and std_logic In vhd
std_logic can help u in optimization process while sysnthesis in some situation if u used the dont-care . also std_logic give u more high-impedance value where u cant get with bit.
For ALU and data path components such as registers, adders and multipliers, bit is good enough.
For bus, FSM control signals and intermodule signals, designers prefer to use std_logic to resolve logical issues.
As someone already said, std_logic offers 8 representations instead of ideal ones from bit.
You try to think about this scenerio,
"If you drive a logic over a bus or a lengthy wire, do you expect ideal 1's and 0's?"
This is why std_logic comes into the picture to resolve issues like this.
You will definetly need to use std_logic in case you want to things like high impedance which is common with buses for example .. u may also need to express don't care and unchanged .. these things can't be expressed if using bit type instead.
I have the same experience of ymq8328. But multiplier is a digital circuit, Does "natural", "integer", "unsigned" and "signed" have any role in this circuit?
Re: what is the diffirence between bit and std_logic In vhd
First of all, these different types make writing, reading and understanding VHDL easier. I know it looks easier to use only one type "std_logic_vector" but the more complex a design gets with signed, unsigned, ranges and floating point the easier these differant types get.