Continue to Site

# What is the difference between x=#5 y and #5 x=y in Verilog?

Status
Not open for further replies.

##### Member level 4
verilog question

Hi,

what is the difference between x=#5 y and #5 x=y

thanks

Re: verilog question

1.
Code:
Sum = (A^B)^C;
#4 T= A & C;
The delay in the seccond statement specifies that the execution of the assignment is to be delayed by 4 time units. That is, after the first statement executes, wait for 4 time units, and then execute the seccond assignment.
2.
Code:
Sum = #3 (A^B)^C;
The delay in this asisgnment means that the value of the right-hand side expression is to be computed first, wait for 3 time units, ant then assign the value to the Sum.

Hope this help,
Rgrds

Points: 2
Re: verilog question

Good explaination!
Also, these two types are defined to simulate trasitional & inertial delays in digital circuits.

Tejas

verilog question

recommand to write the #5 x=y ,seconad statement in your design, is is more fitable the fact.

Re: verilog question

Thank you AMI, wonderfully explained. It is one of the common test in an interview

verilog question

I think the #5 a=b is usually used in the behavior model,is it right?

Re: verilog question

Hi
I think both will give the same effect finally
but we always use the 1st one

Thanks
Haytham

Added after 3 hours 8 minutes:

Mistake found

Sorry
We always use the 2nd one

verilog question

second shows the delay between execution of two statements
while
first shows that when y is computed, there shouild be delay before the assignment is done to x

Re: verilog question

x = #5 y is delay y current value by 5, then assign to x

#5 x = y is delay 5 firstly, then assign y value to x

best regards

Hi,

what is the difference between x=#5 y and #5 x=y

thanks

Re: verilog question

for example, at time 4, y changes from 0 to 3

for "x = #5 y", at time 5, x gets the value of y at time 0, so at time 5, x becomes 0

for "#5 x = y", at time 5, x gets teh value of y at time 5, so at time 5, x becomes 3

Re: verilog question

Hi,

what is the difference between x=#5 y and #5 x=y

thanks
Interesting question, why not you try it in your verilog simulator ,
then you'll find the interesting ans.

Re: verilog question

Hi,

This is just a classic example of inter-segment and intra-segment delay statements.

Thanks,
-Karthik

Status
Not open for further replies.