reg_ic,
If Vss moves by some amount, the current injected from Vss into the ckt is asymmetric because the Nmos has a 1:k ratio. That is, in the first config (amp2), Vgs of M9 and M7 are equal; however, if their source voltage goes down by some amount their drain currents change by 1:k and not 1:1 as is the case with the second config (amp2). This asymmetric injection of Vss current will give rise to a input referred offset if your current gain 'k' of nmos and k of pmos side are not the same, which could be very likely because. That is, DC PSRR- will be degraded. In other words, usually it is a good idea to make your design so that you rely on matching between nmos and another nmos; not between nmos and pmos. You can use the same argument for AC PSRR- because there is a CGS of M9 and M7 that is present that will change their Vgs and will follow changes in Vss. On top of that, CGS of the M8, M6 are different; and you can find similar reasoning as to why PSRR+ will be worse.
hr_rezaee,
Thanks for the explanation. I was assuming a resonably low freq. application. That is why I didnt take into account mirror poles and zeros. However, since we do not know the application of this amp., you are correct.