What is the difference between STA and CTS?

[gmailbond]

What is the difference between STA and CTS when the goal of both the processes is same?Which is given highest priority and why?
Why cant we fix hold time in front end as we do setup and then move on Back end?

 

[D Saurabh]

STA and CTS do not have the same goals. As the names suggest - STA is a timing 'Analysis' step, where we do an analysis using tools such as Primetime to check if the design meets the timing specification. CTS on the other hand is a clock tree 'Synthesis' step - it is a step in the Implementation process of the chip, where the clock tree(s) is inserted into the design to connect a clock(s) to all FF in the design. Unlike regular logic, the clock is a high fanout net and needs special treatment to ensure that it reaches all the FF with minimal skew, latency etc. Hence this is done as a separate synthesis step after regular logic synthesis. Once the clock tree has been inserted, we do what is called a postlayout STA to check if all timing can be met.

-D

 

[ljxpjpjljx]

STA and CTS is two step when doing ASIC!

 

[pradeepkumar481]

hello gmailbond

what ever saurabh has said is absolutly correct. STA only deals with Timing analysis of ur circuit and CTS is w.r.t inserting the clock tree in to u r design and it (The goal of CTS) is used to minimize skew and insertion delay.

Thankyou
Pradeep

 

[raju3295]

adding to the above explanations, before CTS clock is treated as a ideal net, means its not synthesized, so there is no point in doing hold analysis , as clock reaches the both f/fs at the same time.