AlexWan is right, that is a bad coding style when used in combinational logic modeling. Thanks for Alex!
see the code below:
/*
bad coding style example
*/
module adder_t2 (co, sum, a, b, ci);
output co;
output [3:0] sum;
input [3:0] a, b;
input ci;
reg co;
reg [3:0] sum;
always @(a or b or ci)
#12 {co, sum} <= a + b + ci; // bad non-block assignment delay coding style
endmodule
module tb;
reg [3:0] a, b;
reg ci;
wire [3:0] sum;
wire co;
adder_t2 dut (.co(co),.sum(sum),.a(a),.b(b),.ci(ci));
initial
begin
#0 {a,b,ci} = {4'h1,4'h1,1'h0};
#50;
#11 {a,b,ci} = {4'h2,4'h5,1'h1};
#5 {a,b,ci} = {4'he,4'h0,1'h1};
#9 {a,b,ci} = {4'h5,4'h1,1'h0};
#50;
$display("good night");
$stop;
end
endmodule
/////////////////////////////////////////
unexpected behavior will be seen.
after the a/b/ci is changed, the {co, sum} <= a + b + ci; is scheduled at 12 time unit later, before the time is come, any change of a/b/ci will effect the {co, sum}, so the delay is not #12.