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In fabrication of chip as the higher metal layers are being deposited, due to process effcets such as etching, ion implantation, some of the ions get accumulated at the oxide layers. as the layers grow in number there will b path between gate & higher metal layer. when sudden electric discharge takes place, gate oxide break down.........
To avoid :--- 1. reverse bias diodes near sio2
2. Metal layer hopping.
I want to know how the diodes r placed manually in the deisgn??
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