First you need to know that, there is only one VERILOG...
You can have a synthesizable or non-synthesizable codes, and it depends on your aim.. If you need a behavioral model, it's aim is for simulation and you can use simulation-purposed codes..
If you need a structural model, you need to take care of your keywords and structure can be synthesized...
I think that, you heard the simulation models that wrote in verilog is normal verilog..
Because, Verilog is suitable for simulation...
Ilgaz