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Synthesis is a process of converting high level description (HDL) of a design into a optimized gate level representation (Netlist) given a standard cell library and certain design constraints.
This step comes after HDL entry and is performed by a synthesis tool .If you use Xilinx free ISE , a synthesis tool called XST is used easily through the project navicator's graphical user interface. You can download ISE from www.xilinx.com and read the XST guide ,then write vhdl code and double click the synthesis process and look at the log file that you get.
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