Re: static and dynamic
From quicklogic's application notes for static power and dynamic power in FPGA's :
Power Basics
The total power usage of an FPGA device can be broken down to total static power and total dynamic power.
PTOTAL = PSP + PDP
Static power is associated with DC current while dynamic power is associated with
AC current.
Static Power:
The FPGA static power is proportional to the static current ICC the current that flows regardless of gate switching (transistor is ON “biased” or OFF “unbiased”). DC power dissipation can be estimated by the worst-case equivalent equation:
PSP = VCC * ICC
For Eclipse devices VCC = 2.5 V and ICC = 0.140 mA.
PSP = (2.5V)(0.140mA) = 0.350 mW
Dynamic Power:
The FPGA dynamic (or active) power is related to the active current ICC[active] the current that flows when switching takes place (transistor ON “biased” and responds to small-signals).
The AC power dissipation can be estimated by the worst-case equivalent equation:
PDP = VCC *ICC[active]
But ICC[active] = C*(dVcc/dt)
PDP = Vcc*C(dVcc/dt)
PDP = ƒ*C*Vcc²
The above equations illustrate that dynamic power is equivalent to the product of the maximum (or intended) operating frequency, the total switching load-capacitance, and the operating voltage.
The total dynamic power consumption for any FPGA can be broken down to the total power utilized by the internal circuitry and the total power consumed by the device's inputs and outputs. For the Eclipse devices, it can be broken down further to make calculation easier to perform and understand.
In addition to logic cells, Eclipse devices have RAM blocks, ECUs, clock networks, and PLLs.
Depending on your designs, the amount of RAM, ECU, PLL, logic cell, and clock network being used can vary. It is easier to split up the power calculations accordingly.