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Good luck with that, since many (most I've seen) models do a
poor job of emulating subthreshold and junction leakage
and many still ignore gate tunneling current altogether (which
is becoming larger than the others, as tox goes down and
gate / channel planarity / uniformity goes away, like on fins).
Your bit cell being symmetric, you can just take the Idd times
bits for the core (you could verify that "0" and "1" states pull
identical Idd, though in practice aging (see crap technology
reliability rules & development practices) will bake in an imbalance
based on history).
Then you have to add in the sense amps, address demux / mux trees,
transition detectors, any output buffering, any differential-signaling
I/Os' static power and so on. After determining, through some series
of attempts, the worst case (and maybe others like "typical") test
conditions to pick detail data, from.