The host interface SPI is a slave mode SPI:
An interrupt is provided when the transmit FIFO and output serial register (SR) are
both empty
The transmitter and receiver each have independent 1024B FIFO buffers
The transmitter and receiver have individual software-defined 2-byte idle patterns of
0xa7 0xb4
SPI detects synchronization errors and is reset by software
Supports a maximum clock of 6.8MHz (based on HCLK/2 = 54.7MHz as the SPI
source clock)