What is SPI idle pattern

[ussername]

Hello,
I couldn't find anything about (SPI) IDLE PATTERN except this thread. I see the pattern is some byte, and after receiving that the pin won't read any data. Is that right?
Does every bus/port standard possess something like that? And for starting reading data there is the same pattern?

 

[FvM]

In contrast to serial interfaces with embedded clock (like PCie, USB, Ethernet), there's no need for an idle pattern with SPI.

 

[ussername]

Exactly as you say. But I refer to my documentation again (HW_User_Guide, page 32).

The host interface SPI is a slave mode SPI:
 An interrupt is provided when the transmit FIFO and output serial register (SR) are
both empty
 The transmitter and receiver each have independent 1024B FIFO buffers
 The transmitter and receiver have individual software-defined 2-byte idle patterns of
0xa7 0xb4
 SPI detects synchronization errors and is reset by software
 Supports a maximum clock of 6.8MHz (based on HCLK/2 = 54.7MHz as the SPI
source clock)

 

[FvM]

As far as I see, it's a device specific protocol, not related to SPI in general.

 

[ussername]

I don't fully get it - the device transmit/receive that byte at the end of the message, and the data exchange stops, while the chip select is still active. So what is it good for? For receiver to know the end of the message? I thought this is made through synchronization with serial clock signal.

 

[ussername]

Or does it simply has the same function like CHIP SELECT, only "software" implemented?