what is spare cells in P&R ?

[vamsi_addagada]

what is spare cells in P&R ?what is that use?

 

[S.Nikhil]

Spare cells like nand, nor gates are spread over the entire chip in p&r. At the final stages of the design, we find that some gates are not working appropriately or if we need to add extra logic to the design, we can make use of these spare cells by connecting them as requd to derive the reqd. additional functionality to the circuit.

thx

S.Nikhil

 

[raju3295]

yes, the spare cells are spread around the chip before signoff and will be used if any extra logic is need to be inserted, it is basically reduces the cost required to prepare the masks while fabrication as only we need to change the metal layers.

 

[wkong_zhu]

Spare cells are used for ECO.
In most IC, first cut work is not realistic. So prepare spare cells(also called dummy cells) for ECO.

 

[Nir Dahan]

I ran a post on spare cells on my blog - Adventures in ASIC Digital Design"
https://asicdigitaldesign.wordpress.com/
the post can be found here:

https://asicdigitaldesign.wordpress.com/2007/11/26/spare-cells/

I also discussed a real world example of a metal fix using spare cells, this can be found here:
the problem:
https://asicdigitaldesign.wordpress.com/2008/01/03/real-world-examples-1-the-dbi-bug/
the solution:
https://asicdigitaldesign.wordpress.com/2008/01/07/real-world-examples-1-dbi-bug-solution/
hope this helps,

Nir
https://asicdigitaldesign.wordpress.com/