what is setup and hold in flip flop Design

[mail4idle2]

what is setup and hold in flip flop Design

 

[barry]

setup time is the time for which the data must be stable at the D input before the clock edge; hold time is the time for which data must be stable AFTER the clock edge.

 

[mail4idle2]

No from Digital Design point of view, from circuit level of point.

 

[hoanglongroyal]

hi mail4idle2,
I think you need some concept about metastability of filpflop
you can refer : https://www.asic-world.com/tidbits/metastablity.html

 

[FAbouzeid]

No from Digital Design point of view, from circuit level of point.

Flip-FLop are made of 2 latches.


Setup is equivalent to the time needed to write a new data in the master latch before clock signal. If you violate the setup time, the previous data will remain in the Master latch.
Hold time is the time needed to avoid a new data to be written in the slave after clock signal. If you violate the hold time, the new data will be captured and transmitted by the flip-flop, instead of the stored one.