What is multi-cycle path?

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faye_hongdou

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multi cycle path

What is a multi-cycle path, and how can I determine wither a path is a multi-cycle path.
 

multicycle path

if u have a big combinational logic in ur design which will never run at ur required frequency...
u have 2 options

1)Add pipeline stage(s) to divide the logic into single-cycle paths
2. Ease off the single-cycle requirement: allow more clock cycles using set_multicycle_path command.

DC will allow more clock cycles for path delay when checking for setup/hold violations...when u specify a path as multicycle path


rgds
 

multi-cycle path

Usually DC/PT check path timing in one cycle.
If you have a path in your design ,which cannot finished operation in one cycle, you can tell DC/PT this path is a multi cycle path.
At same time, you should guarantee that output of this path can be correctly flopped by next stage.
It's designer's responsibility.
 

set_multicycle_path

Ye, it's up to the designer whether the path is multi-cycle path according the the synthesis ability about the max frequency may be achieved.
one import thing is the hold timing for the multi-cycle path, it should be the setup_cycle-1
 

multi cycle paths

One path that need multi cycle to complete
 

multi-cycle paths

how I can decide the time checked for the setup/hold time? for example the circuit must be 3 clocks. what's the setup time? and what's the hold time?
 

what is multi cycle path

how I can decide the time checked for the setup/hold time?
This depends on the flop that is used and the library vendor datasheet should give you the setup and hold times
 

multicycle paths

the multi-clock path is defined in design specification. if you don't kown which is multi-clock path in design process, usually use PT to check path timing in one cycle.
 

what is multicycle path

how I can decide the time checked for the setup/hold time? for example the circuit must be 3 clocks. what's the setup time? and what's the hold time?

For PT, your setup time requirements for the multicycle path is 3 clock cycle, if you constraint the path to:
set_multicycle_path 3 -setup -from <> -to <>
PT by default will check your hold time at 3-1 clock cycle.
However, you can specify the hold time check to be checkat clock 0 as below:
set_multicycle_path 2 -hold -from <> -to <>
 

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