If Test clock does not reach flip-flop, then during atpg, when tclk toggles, the flip-flop will not be able to scan data through the flip-flop. That is why you are getting "uncontrollable clock input of flip-flop violation". This error is usually there if clock divider is used or some other logic is used to drive the clock pin instead of directly using the clock.
One way to fix it just use the mux to bypass the logic and select the tclk while in test_mode, else functional clock will be used.