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Four-pin (plus power/ground) interface designed to test connections between chips. Interface is serial (clocked via the TCK pin). Configuration is performed by manipulating a state machine one bit at a time (via TMS pin), then transferring one bit of data in and out per TCK clock (via TDI and TDO pins, respectively). Different instruction modes can be loaded to read the chip ID, sample input pins, drive (or float) output pins, manipulate chip functions, or bypass (pipe TDI to TDO to logically shorten chains of multiple chips). Operating frequency varies per chip, but is typically 10-100MHz TCK (10-100ns per bit time). K Kb Kilobits (Note that storage (RAM, disc) is usually measured in binary thousands, i.e., 1,024 bits.)
Some of the RISC CPU can also make use of the built-in JTAG port to download program into its on board memory for SW development and debugging. It does not only use for testing connection between chips.
Some embedded systems also use it to program its on-board FLASH memory for firmware reprogramming.
For FPGA design & development, it is the main connection to download the programming bit stream into its internal configration SRAM.
Can any one explain JTAG timing? i.e. how does the timing diagram looks like between tck, tdi and tdo?
All the papers here are useless as they do not explain this main issue.
Generally the IEEE standard defines a functional timing. It says, which performance specifications have to be given by manufacturers, e. g. TCK setup and hold, TDO delay. Chip vendors often show complete timing diagrams, see a figure from an Altera FPGA manual.
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