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Hot electron is kind of a misnomer. Holes are the real
nuisance. People generalize to "hot carrier effects".
A carrier with greater than thermal energy can get to
tunneling. If it leaves the silicon and lodges in the near
oxides, you get both trapped charge and probabilistic
damage or activation of passivated traps / states. The
threshold voltage and surface mobility (gm) are hurt.
You can impart superthermal energy by high field and
you can direct the carriers to an unfortunate stopping
location by vector field sum. Typically VG=VD/2 is about
the worst, strong drain potential / field sum and a gate
bias that pulls the loose carriers up into the spacer oxide.
You reduce it by running lower supply at longer channel,
"drain engineering" to stand off field at greater distance
from the gate / spacer, better quality oxides that have
fewer traps, circuit design that avoids peak HCE stress
or transitions through that region as quickly and
infrequently as possible (everh switching event in digital
spends a tiny slice of time in that region; analog might
camp out, which would be bad).
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