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what is function of the PMOS between the op-amp two stages?

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fightshan

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The op-amp has a typical two-stages structure,it works in open-loop as a comparator, my puzzle
is why the PMOS MP3 is bridged between the two stages?what is the function of the MP3?
(4/2 or 3/0.7 means W/L=4μ/2μ or 3μ/700nm, and m=multiple(s))
thank you!
 

For the first look, this MP3 fet is used to preventing cut-off of a MP2 when the output is in low state.
 

For the first look, this MP3 fet is used to preventing cut-off of a MP2 when the output is in low state.
Yes, apparently a clamp circuit for the MN3/MP2 drain node to speed up comparator switching.
 

Yes, apparently a clamp circuit for the MN3/MP2 drain node to speed up comparator switching.

Thank you for your reply. The following is my understanding.
when the output is in low state, the drain of MN3/MP2 will be in high voltage,so the MP3 (acts like a switch) will breakover and the gate voltage of MN3 has a tendency to become high ,that is to say, MN3 has a tendency to breakover and the Vds of MN3 has a tendency to become low, so finally, MP3 connects a negative feedback loop between the drain and gate of MN3. The function of MP3 makes the MP2/MN3 drain can not achieve a high voltage
approaching VDD, so the MN2 will not cut off and the comparator switching is speeded up.
Is any problem with my understanding? thanks again.

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For the first look, this MP3 fet is used to preventing cut-off of a MP2 when the output is in low state.

Thank you for your reply.
when the output is in high state, that is MP2/MN3 drain is in low voltage, the MP3 will not work, is that right? and is MP3 only beneficial for the speed of high-state conventing to low-state? what about the opposite process?
 

Can you plot input/output characteristics of this comparator with and without the MP3 transistor ? Also it is interesting the waveform of the node before the output inverter.
 

Can you plot input/output characteristics of this comparator with and without the MP3 transistor ? Also it is interesting the waveform of the node before the output inverter.
You mean I need analyze the small-siginal characteristics?
I did the simulation using Cadence spectre, I think the simulation result validate what I guess as above。

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Yes, apparently a clamp circuit for the MN3/MP2 drain node to speed up comparator switching.
simulation result.png
I simulated the comparator using Cadence spectre.(in this picture, Vout is MN3/MP2 drain but not the "Vout' in the first picture)
the left is the result with MP3, Vout=4.718V ,so MP2 will not be cut off.
the right is the result without MP3, Vout=5V, obviously MP2 will be cut off.
 

The clamping effect can be clearly seen.

I presume you must perform the simulation in a different speed range to see a relevant effect on comparator response time. Obviously it also depends on the transistor parameters, e.g. capacitances.
 

You mean I need analyze the small-siginal characteristics?
No I meant the transient simulation which you had already provided.

I see the difference but I do not sure about the "speed" of the comparator as mentioned in the above posts.
I see that the output signal has more sharper transitions then w/o MP3 transistor.
Can you also measure the delay from the input to the output for the both cases ? Also it is interesting the detection threshold of the comparator.
How much voltage difference the comparator amplifies.
 

The clamping effect can be clearly seen.

I presume you must perform the simulation in a different speed range to see a relevant effect on comparator response time. Obviously it also depends on the transistor parameters, e.g. capacitances.

actually,I am not sure how the clamping circuit to speed up the comparator, can you tell me more?
 

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