what is difference of SRAM and Synchronous Rigster File ?

[atuo]

When I design a IC , I use the ram on chip. I find the foundry provide the SRAM and Rigster File generator, but I want to know what is difference of SRAM and Synchronous Rigster File, and I should select SRAM or Rigster File ?

 

[armer]

Re: what is difference of SRAM and Synchronous Rigster File

For big memory, i offen use sram. For small memory, i offen use regfile.
By the way, the access process is different between sram and regfile.

 

[atuo]

Re: what is difference of SRAM and Synchronous Rigster File

How many memory is big? and can u tell me what difference of access process ? thanks.

 

[maxnil]

Re: what is difference of SRAM and Synchronous Rigster File

How many memory is big? and can u tell me what difference of access process ? thanks.

For the process we use (Infineon .13um), they say that if a memory is smaller than 1kbit, then we should use registers. A normal memory often uses a BIST-controller for production test. A BIST controller does not differ much in size for different memory sizes, so a very smal memory will still need a rather big (>2 Kgate depending on functionality) BIST controller, this controller may be bigger than the actual memory array.
A registerfile does not need any memory-BIST, it will be testet through the normal scan-chain.

 

[maxnil]

Re: what is difference of SRAM and Synchronous Rigster File

How many memory is big? and can u tell me what difference of access process ? thanks.

A singel port SRAM can not be both read and written to in the same clock cycle.
A two port SRAM have one read port (raddr + rdata) and one write port (waddr + wdata), the two ports also have seperate clocks, which makes it very suitable for FIFOs between two different clock domains.
A dual port SRAM have two separate read/write ports (2 x addr/rdata/wdata). A dual port SRAM is often twice as big area as a single port SRAM.
A register file can be implemented in many ways, it can have the interface of a single port SRAM or a two port SRAM.
One big advantage of the register file is that it can be implemented with as many read ports as you want.
So a single or two port SRAM can very easy be replaced with a Register file (with the right implementation).

 

[optor]

Re: what is difference of SRAM and Synchronous Rigster File

Anyway, I think SRAM is much compact that register file. While the access time of register file is much shorter than SRAM.

 

[atuo]

Re: what is difference of SRAM and Synchronous Rigster File

but the Rigster File also need memory BIST

 

[sunjimmy]

Hi,

As far as i know, register file is composed of DFF. So its speed is much faster than SRAM. Usually it is used for high-speed cache. But SRAM can provide higher density, so it's mainly used as data buffer.

Hope it helps : )

 

[tom123]

Re: what is difference of SRAM and Synchronous Rigster File

sram has a ram array and a ring of sense amplifier.

synchronous are regular DFF architecture and some decoding logic.

when you require larger memory, SRAM has less area than register file;

when you require less memory, register file has less area than SRAM.

because sram has sense amplifier that consume fairly large area.

best regards

When I design a IC , I use the ram on chip. I find the foundry provide the SRAM and Rigster File generator, but I want to know what is difference of SRAM and Synchronous Rigster File, and I should select SRAM or Rigster File ?

 

[zeese]

Re: what is difference of SRAM and Synchronous Rigster File

So, when someone says, data buffer, does it means,
it could be either register(DFF) or RAM?

In verilog coding, does it have different coding style
to refer to data buffer using registers and to refer to RAM?

In verilog, if I declare

reg [7:0] memory[0:1024]

If the design goes to synthesis or layout, will it become dff data buffers
or RAM?

Please help. Tq

 

[eda_wiz]

Re: what is difference of SRAM and Synchronous Rigster File

So, when someone says, data buffer, does it means,
it could be either register(DFF) or RAM?

In verilog coding, does it have different coding style
to refer to data buffer using registers and to refer to RAM?

In verilog, if I declare

reg [7:0] memory[0:1024]

If the design goes to synthesis or layout, will it become dff data buffers
or RAM?

Please help. Tq

if u declare " reg [7:0] memory[0:1024]" in verilog it will be just registers. Not registerfile and not SRAM. If u want to use RegisterFile or SRAM , you have to use the memory compiler software supplied by the process vendor.

rgds