What is clock gatting ?

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naveen_zs

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How do i can make differer between a clock gatting gate (for ex : NAND) to simple gate
note :if i have used a synopsys DC tool to synthesis
 

Hi Naveen,
If your library have Clock Gating cell, then DC can infer clock gating automatically(if you enable clock gating in your synthesis).
 

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    naveen_zs

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viju said:
Hi Naveen,
If your library have Clock Gating cell, then DC can infer clock gating automatically(if you enable clock gating in your synthesis).
Click to expand...

Thanks Viju

I just refrain my question to a very clear manner (my doubt is analyzing reports in PT- STA)

I am seeing violations of 30 + ns (12 ns is my design - clock period)
when i switch on CLOCK gatting ON in PT ,
How i can interpret whether that is valid or not
 

it may generate clock delay
so the high speed cell should not set clock gating

that just i think
 

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