Re: AMBA question
A conventional interleaved memory provides an "even" memory bank and an "odd" memory bank. Data having even memory addresses are stored in the even memory bank. Data having odd memory addresses are stored in the odd memory bank. Hence, any two sequential memory locations are stored in separate memory banks. If the two sequential memory addresses are to be accessed, a first memory location is read from the first memory bank and, while the first memory bank is read, the second memory bank is pre-charged. Then, the second memory location is read from the second memory bank, while the first memory bank is pre-charged. Hence, if two sequential memory locations are accessed, the data stored at the locations may be fetched quickly without any intervening pre-charge cycles required for typical random access memory.
Added after 1 minutes:
Burst mode sequences are typically either "linear sequential" (e.g., AMD, and Motorola burst sequences) or "aligned sequential" (e.g., Intel burst sequences), and may have a burst address space of any size, although four-word and 256-word burst address space sizes are typical. For memory chips to be used for burst mode access, burst mode processing circuitry is provided directly on the memory chip. More specifically, a means is provided directly on the chip for loading the initial address, generating sequential addresses within the burst address spaces, and accessing the data at the initial and sequentially-generated addresses, based on a predefined burst mode sequence and burst addressing space size