Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] What is a read latch and Write latch in processor/controllers device operations?

Status
Not open for further replies.

pjamu

Newbie level 4
Joined
Jan 29, 2013
Messages
7
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,327
I came across timing diagrams with 2 different aspects-
    • One with 'Write latch set'
    • Another With 'Write Latch 'not set.
What does 'Write Latch' mean?


Also what is the double "S" in timing cycles?( In the file attached)
timing diagram.PNG
 

Most memory bus set ups, require that a pin called "write" must be set for the duration of the writing process. With a write latch, the write control signal just pulses the "set" line and at the end of the writing process, then pulses the write "not set" line.
The SSs, just show an indeterminate time, the space between the Ss, can be of any time period.
Frank
 
  • Like
Reactions: pjamu

    pjamu

    Points: 2
    Helpful Answer Positive Rating
Thank you. That was concise.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top