What is a 'gate coupling' from semicon design point of view?

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dog2mari

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my question is what a 'gate coupling is" and how it is related to GIDL?

ASAP please... please
 

Re: What is a 'gate coupling' from semicon design point of v

GIDL: Gate Induced Drain Leakage.

GIDL currents arises in the high electric field under the gate/drain overlap region. GIDL occurs at a low gate voltage Vg and high drain Voltage Vd and generates carriers into the substrate and drain from surface traps.

(taken from: Kaushik Roy :"Low Power CMOS VLSI Circuit Design")
 

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