verilog override timescale
In Verilog, compiler directives, like `timescale, apply across file boundaries. The directive is in effect until it's overridden by a subsequent `timescale compiler directive.
For example, consider the following 3 files:
a.v
====
`timescale 1ns/1ns
module A;
...
endmodule
b.v
===
`timescale 1ps/1ps
module B;
...
endmodule
c.v
===
module C;
...
endmodule
So, if you compile these files in the order
a.v b.v c.v
then module C will have a timescale of 1ps/1ps, the same timescale as module B which appears before it in the file order on the command line.
If you compile these files in the order
a.v c.v b.v
then module C will have a timescale of 1ns/1ns, the same timescale as module A which appears before it in the file order on the command line.
To avoid this file order dependancy and the problems that could result from it, it's highly recommended to include a timescale directive in every Verilog source file.