What happened in this telescope stage?

[moo]

Hello, I've made a cascode stage for an opamp. However I find the frequency response is far from good stability. From the Bode plot, the phase margin is 37.76 deg.

According to the shape of the frequency response, how many poles and zeroes are there existing?
And how can I optimize the phase margin?

Thanks!

 

[moo]

I feel a little puzzled to the Bode plot. There seems to exist a pole-zero doublet. Is it right?

 

[laglead]

From bode plot this circuit has 4 poles and 3 zeros, among which there is a pole-zero doublet. It is probably due to the direct coupling of M3b's gate-drain capacitors. Remember, your M3b and M3a will probably work in linear region. their gate-drain capacitor may be big.
Recommend using small bias resistor in the circuit.
Use cap load on the output to make compensation.

 

[willyboy19]

M3a and M3b should operate in saturation region to achieve the required DC gain (that is exactly the reason why using a telescopic OTA). Make sure all the transistors operate in saturation region and put 2~3 pF compensation/load capacitor and re-run the simulation. You should be able to get around 60 degree of phase margin depends on your loop gain.

 

[jutek]

hello

how much current does it consume?

regards

 

[laglead]

Try smaller bias resistors, which can bring M3a and M3b into saturation.

 

[moo]

To laglead and willyboy19

Thank you.

I checked my netlist again and changed the bias res. I got an improved DC gain of 79.4dB. However, the resistor value is changed from 8k to 12k( different from laglead's suggestion, WHY?) . The operation points before and after the change are listed:

bias res=8k | bias res=12k
M3a M3b M4a M4b | M3a M3b M4a M4b
Vgs(mV) -832 -832 -839 -839 | -832 -832 -834 -834
Vth(mV) -604 -604 -604 -604 | -604 -604 -604 -604
Vds(mV) -603 -647 -236 -236 | -489 -741 -345 -346

The gain improvement can be explained by better operation points. However, phase margin doesn't change although all transistors are in saturation. The new Bode plot with 12k bias res is given.

At last I put a 2pF load cap at the output ( according to willyboy19's suggestion). It is effective and I got a 71deg phase margin( shown in the attachment too).
BUT it means that there is the constrain of the load cap range if the single-stage opamp is used. If we'd want to make it conditionlessly stable, we will have to deel with the nondominant poles and zeroes.
What can I do in my case?

Thank you.

 

[moo]

To jutek

the single stage consums 56uA totally

 

[laglead]

Hi, moo,
I copy your 2nd simulation data here:

bias res=8k | bias res=12k
M3a M3b M4a M4b | M3a M3b M4a M4b
Vgs(mV) -832 -832 -839 -839 | -832 -832 -834 -834
Vth(mV) -604 -604 -604 -604 | -604 -604 -604 -604
Vds(mV) -603 -647 -236 -236 | -489 -741 -345 -346

M3a enter linear legion deeper. But M4a and M4b are more saturate than before.
Your higher DC gain comes from the saturation of M4a and M4b, but at the cost of worse M3a's bias condition. M3a and M3b are not balanced anymore, which is not good for a mirror. Linear-biased M3a will have bigger cap. Note, this cap is NOT on the dominat pole. This will lead to bad frequency response. Please check your posted diagram. In the first simulation you got phase margin 37.76deg at -0.884db (631MHz). In the second time you got phase margin 37.85 at -0.458db. So your second design may have worse phase margin at 0db point. So, changing resistor value alone cannot guarantee your transistor in saturation. You should change transistor size as well to get a good dc point. The choise of resistor value depends on bias current.