Hi, moo,
I copy your 2nd simulation data here:
bias res=8k | bias res=12k
M3a M3b M4a M4b | M3a M3b M4a M4b
Vgs(mV) -832 -832 -839 -839 | -832 -832 -834 -834
Vth(mV) -604 -604 -604 -604 | -604 -604 -604 -604
Vds(mV) -603 -647 -236 -236 | -489 -741 -345 -346
M3a enter linear legion deeper. But M4a and M4b are more saturate than before.
Your higher DC gain comes from the saturation of M4a and M4b, but at the cost of worse M3a's bias condition. M3a and M3b are not balanced anymore, which is not good for a mirror. Linear-biased M3a will have bigger cap. Note, this cap is NOT on the dominat pole. This will lead to bad frequency response. Please check your posted diagram. In the first simulation you got phase margin 37.76deg at -0.884db (631MHz). In the second time you got phase margin 37.85 at -0.458db. So your second design may have worse phase margin at 0db point. So, changing resistor value alone cannot guarantee your transistor in saturation. You should change transistor size as well to get a good dc point. The choise of resistor value depends on bias current.