Re: CMOS technology
Dear Hackson,
As you have questioned about 0.13µm technology, it's actually 0.12µm (to be exact). 0.12µm is specified for the Poly-Si Gate of a MOS transistor in the HCMOS 9 Technology officially adopted since 2000 by all foundaries and IC Fabrication Facilities.
As you can see, it only specifies the Poly-Si Gate of a MOS Transistor, i.e. only the Masked Gate Length. Thus not the Effective Gate Length, which is subjected to Lateral Diffusion on either side of the channel in the 7-layer CMOS Process of a HCMOS 9 Technology. If to use the Effective Gate Length as a standard, this will make the control of CMOS process too difficult to manufacture millions of MOS transistors on the same wafer at a high yield by any IC Fabrication Facilities.
For over the past decade, all Digital ICs are designed using CAD Software on workstations. Designs are subjected to Grids and Pitches specified in a chosen HCMOS Technology. In this manner, the physical layout of an IC design can be produced in a universal or standard specifications so that it can be manufactured the same way anywhere, from North America, Europe and Asia.
Before 0.12µm, there were 0.25µm and 0.5µm. All these are collectively known as the Lambda-based designs that were widely accepted since 1985 used in the IC community. This further promotes Design Re-use Concept.
PhD (Imperial College London)
IC Design Engr. Analog Devices Plc. (Ireland)