A VHDL or Verilog simulator (Vivado simulator) initializes all variables/signals/reg values to U at simulation start. This is not the same as something like C which will have whatever was left over in memory at the time the variable was allocated until you initialize it.
In this case the values are a VHDL real type with the value either initialized to those values sometime after 0ns or were assigned those values by some assignment statement.
Actually, VHDL only does the 'U' initialization for std_ulogic and types derived from std_ulogic. What the LRM says is to initialize signals and variable to the 'first' value in the type (I'm paraphrasing a bit). The 'U' value in std_ulogic is located in the first position of the definition of the type std_ulogic. Signals/variables that are reals, integers, naturals, user defined types do not get this uninitialized 'U' value, they get a value that depends on the type.
signal SomeReal: real; -- Will initialize to a really big negative real value
signal SomeInteger: integer; -- Will initialize to a really big negative integer value
signal SomeNatural: natural; -- Will initialize to 0
signal SomeNatural: positive; -- Will initialize to 1
type MyType is (Red, Green, Blue);
signal SomeMyType; -- Will initialize to 'Red'
Since the OP posted the value as being 6.40690750792007e+71, that value cannot be the result of an uninitialized signal of type real.
Kevin Jennings