Re: ? in Verilog
I have a simple doubt in verilog,
what does this statement mean
assign Full=(wrptr > 4'b1111)?1'b1:1'b0;
I don't get the'?' mark part.
"?" is called a ternary operator because it works on not two but THREE operands( wrptr > 4'b1111 actually evaluates to True or False which is in turn taken as the third operand).If the expression before the "?" evaluates to true then the value immediately following the "?" is assigned to the variable(here, Full) otherwise if its false the value after the ":" is assigned.
This ternary operator is the most simple way of implementing a MUX ..
By nesting the ternary operators, we can actually implement n:1 MUX ..
Regards
Kaustubh