RTL- A kind of hardware description language (HDL) used in describing the registers of a computer or digital electronic system, and the way in which data is transferred between them. 2. An intermediate code for a machine with an infinite number of registers, used for machine-independent optimisation
RTL stands for Register Transfer Language. It is basically used to denote the transfer of information in registers. HDl is language for computer simulation purposes. RTL has no relation to Computer simulation.
If the HDL(dataflow/structural/behavioral/any othercombination) is synthesizable, then the design is implimentable in hardware. So that the synthesizable HDL(dataflow/structural/behavioral/any othercombination) is called RTL model.
If something that is synthsizable is called RTL, then what about languages like HandelC and others that claims beeing high level synthesizable languages? Are they RTL? Are they hidgh level?
VHDL, Verilog HDL, HandelC, etc. These are all high level languages. A high level language program, which is sinthesizable is called an RTL model. If the high level language program is not sinthesizable, then we can't impliment the design in hardware, so that it can not be an RTL model.
RTL description is more complex and less technology dependent than behavior hardware description.
RTL description is less complex and less technology dependent than transistor level description.
With behavior description you can easy describe complex sistems as memories, ALUs, and etc. For 32-bit adder description you need only simple equation Z=X+Y where X,Y and Z are 32-bit vectors. This kind of description is very easy for simulation.
Simulation of previous example in RTL is more complex and requires more processor time.
Transistor level simulation with HSPICE is very complex and requires powerfull processing unit.
RTL stands for Register Transfer Level. It's a behavioral design concept in which you make HDL models of registered circuits and how signals interact between them such as memories, flip flops, latches, shift registers, and so on. As many people said, they are fully synthesizeable, because they are written using basic HDL structures (not functions or fancy things). The IEEE 1076 recomendation is a good reference to understand the RTL concepts (in VHDL).
And also the IEEE 1364.1 (verilog recommendation for RTL synthesys):
rtl is register transfer logic.....basically it can be behavoral or data flow but should be synthesizable.......main stress will going for rtl level modeling is how data will flow between various stages of a design separated by registers(flops or latches).......