lec sample script
Hi Arthur,
LEC is nothing but Logic Equivalence checking.. LEC can be done with Conformal, Formality, Formal PRo tools..
It is basically checking functionality between RTL and Netlist... and also you can check the functionality between pre-layout netlist and post layout netlist just to make sure that P&R tool didnt goofed up anything...
Pls find the sample script to run LEC,
set system mode setup
set log file ddc.log -replace
read library -Both -sensitive -Verilog <std_Cells_verilog_file>
read design <original netlist > -Verilog -Golden -sensitive
read design <post_layout netlist > -Verilog -Revised -sensitive
# Also read memory .v if u have any
add black box <mem_name> -both
add black box <mem_name> -both
set system mode lec
add compare points -all
compare
You can follow the flow from the userguide of Conformal which is from Cadence..
Hope this helps you,
Regards,
Pinkesh